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| U3770M CT2 I/Q Modulator and Clock Circuitry Description U3770M is a quadrature modulator realized with MATRA MHS' advanced 0.8 micron CMOS process. The IC is especially designed for CT2 application in conjunction with TEMIC's RF/IF signal processor U2760B and a CT2 baseband controller (i.e., AMD PhoXTM controller Am79C4xx). Together with TEMIC's PLL IC U2783B and the GaAs front end U7001BG, a complete CT2 chip set is available. Electrostatic sensitive device. Observe precautions for handling. Features D Programmable 0.8/1.6 MHz quadrature modulated carrier generation D Supply voltage range 2.7 to 3.3 V D Low power consumption, typical 12 mW D SO16 package or die form D More than 26 dB LO and sideband suppression D 18.432 MHz CMOS level clock generation Block Diagram RRef in 12.8 MHz 2 DIV / 25 Phase comparator 512 kHz LF 11 VCO 14 CLK out 95 9881 Amp. 3 4 13 12 10 6 5 8 7 1, 15, 16 DNC DIV / 2 or DIV / 4 6.4 MHz 3.2 MHz 512 kHz DIV / 36 18.432 MHz VDD DGND AGND PROG TST Qin QBin Iin IBin Dual DFF 9 MOD out Figure 1. Block diagram MATRA MHS Rev. A2, 03-Dec-97 1 (5) U3770M Functional Description U3770M has been designed to reduce power consumption and cost of CT2 devices. An innovative CMOS I,Q modulator with an extremely low current provides all the advantages of I,Q modulation: - No requirement for FM deviation tuning - Eliminates the Gaussian filter - Simplifies the power ramping control The modulated output carrier can be programmed to be 0.8 MHz or 1.6 MHz by the PROG control pin. The typical supply voltage is 3 V @ 4 mA. To reduce overall system cost, an internal PLL generates a 18.432 MHz clock signal from the system 12.8 MHz reference oscillator. This way, only one crystal oscillator is needed in the complete CT2 device. Internally, the 12.8 MHz reference signal is fed into a shaping amplifier and then into two logic dividers, to generate a 512 kHz and a programmable 3.2 or 6.4 MHz clock. This clock is divided by 4 by two D flip-flops. The flip-flop outputs drive the four analog switches in quadrature. A pair of analog switches make a local oscillator (LO) suppression mixer. By summing the other pair outputs, we obtain both LO and sideband suppression, of more than -26 dBc. The 512 kHz clock drives a frequency synthesizer. The VCO runs at a fixed frequency of 18.432 MHz. The VCO control voltage (LF pin) controls the VCO frequency. Pin Description DNC FRef in 1 2 16 DNC 15 DNC 14 CLKout 13 AGND 12 PROG 11 LF 10 TST 9 MODout 95 9930 Pin 2 3 4 5 6 7 8 9 10 11 12 13 14 1, 15, 16 Symbol FRef in VDD DGND QBin Qin IBin Iin MODout TST LF PROG AGND CLKout DNC VDD 3 DGND 4 QB 5 Q6 IB I 7 8 Function External 12.8 MHz reference frequency input Supply voltage Digital ground Analog switches input Analog switches input Analog switches input Analog switches input Modulator output signal Test input, must be connected to GND (only factory use) PLL loop filter PROG = 0, 1.6 MHz mode PROG = 1, 0.8 MHz mode Analog ground Digital CMOS clock output 18.432 MHz Do not connect Figure 2. Pinning 2 (5) MATRA MHS Rev. A2, 03-Dec-97 U3770M Absolute Maximum Ratings Stresses at or above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in this data sheet is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Supply voltage Modulator input voltages Reference frequency input Ambient temperature Storage temperature Junction temperature Symbol VDD I IB Q QB FRef in Tamb Tstg Tj Value 6 -0.5 to VDD Unit V V -0.5 to VDD -40 to +85 -65 to +150 Tj < Tamb +10 V C C C Operating Range Parameters Supply voltage Ambient temperature Junction temperature Storage temperature Symbol VDD Tamb Tj Tstg Value 3 10% -5 to +70 Tj < Tamb +5 -40 to +125 " Unit V C C C Electrical Characteristics Test conditions (unless otherwise specified) related to test circuit VS = 3 V, VBIi, VBIi and VBQi, VBQi = 1 VPP single ended, oscillator frequency FRef in = 12.8 MHz, Tamb = -5 to +70C Parameters Supply voltage range Supply current FRef in Input voltage Input impedance I, Q inputs Input voltage Input impedance Input frequency External bias voltage MODout Output level 1) LO and sideband suppression Output impedance CLKout Output frequency Output voltage swing Note 1) Test Conditions / Pins Pin 3 Pin 3 Pin 2 Symbol VDD IDD VF Ref in ZF Ref in Pins 5, 6, 7 and 8 Single ended Single ended VIin, Qin ZIin, Qin FIin, Qin VIB, QB VMod out LO sub SB sub ZMod out Pin 14 @ load = 20 pF FCLK out VCLK out 18.432 1.8 MHz V Min. 2.7 Typ. 3 4 Max. 3.3 Unit V mA mVPP kW 1 20 18 1.5 70 -26 5 VPP kW kHz V mVRMS dBc kW 150 100 Pin 9 Unloaded The output signal contains some harmonics, to be filtered by an external low-pass filter MATRA MHS Rev. A2, 03-Dec-97 3 (5) U3770M Test Circuit 4.7 nF 22 W 11 DIV / 25 Phase 512 kHz comparator VCO 14 CLK out 47 nF R Ref in 12.8 MHz 2 LF 95 9967 3 VDD DGND AGND PROG TST 4 13 12 10 Amp 512 kHz DIV / 36 18.432 MHz DIV / 2 or DIV / 4 6.4 MHz 3.2 MHz Dual DFF 9 MOD out 6 Q in QB in 5 I in 8 IB in 7 1 nF 1 kW 1 kW 1 nF 1 kW 1 nF 1 kW 1 nF Figure 3. Test circuit 4 (5) MATRA MHS Rev. A2, 03-Dec-97 U3770M Package Information Package: SO16 We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC products for any unintended or unauthorized application, the buyer shall indemnify TEMIC against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. TEMIC TELEFUNKEN microelectronic GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 ( 0 ) 7131 67 2831, Fax number: 49 ( 0 ) 7131 67 2423 MATRA MHS Rev. A2, 03-Dec-97 5 (5) |
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